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2007 Microchip Technology Inc.

Preliminary

DS70165E-page 133

dsPIC33F

6.4

Interrupt Setup Procedures

6.4.1

INITIALIZATION

To configure an interrupt source:

Set the NSTDIS bit (INTCON1<15>) if nested

interrupts are not desired.

Select the user-assigned priority level for the

interrupt source by writing the control bits in the

appropriate IPCx register. The priority level will

depend on the specific application and type of

interrupt source. If multiple priority levels are not

desired, the IPCx register control bits for all

enabled interrupt sources may be programmed

to the same non-zero value.

Clear the interrupt flag status bit associated with

the peripheral in the associated IFSx register.

Enable the interrupt source by setting the inter-

rupt enable control bit associated with the

source in the appropriate IECx register.

6.4.2

INTERRUPT SERVICE ROUTINE

The method that is used to declare an ISR and initialize

the IVT with the correct vector address will depend on

the programming language (i.e., C or assembler) and

the language development toolsuite that is used to

develop the application. In general, the user must clear

the interrupt flag in the appropriate IFSx register for the

source of interrupt that the ISR handles. Otherwise, the

ISR will be re-entered immediately after exiting the

routine. If the ISR is coded in assembly language, it

must be terminated using a RETFIE instruction to

unstack the saved PC value, SRL value and old CPU

priority level.

6.4.3

TRAP SERVICE ROUTINE

A Trap Service Routine (TSR) is coded like an ISR,

except that the appropriate trap status flag in the

INTCON1 register must be cleared to avoid re-entry

into the TSR.

6.4.4

INTERRUPT DISABLE

All user interrupts can be disabled using the following

procedure:

Push the current SR value onto the software

stack using the PUSH instruction.

Force the CPU to priority level 7 by inclusive

ORing the value OEh with SRL.

To enable user interrupts, the POP instruction may be

used to restore the previous SR value.

Note that only user interrupts with a priority level of 7 or

less can be disabled. Trap sources (level 8-level 15)

cannot be disabled.

The DISI instruction provides a convenient way to dis-

able interrupts of priority levels 1-6 for a fixed period of

time. Level 7 interrupt sources are not disabled by the

DISI

instruction.

Note:

At a device Reset, the IPCx registers are

initialized, such that all user interrupt

sources are assigned to priority level 4.

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